A wafer level scan is a test method used to discover timing faults in digital logic at the wafer probe level. Scan testing can be used to test the timing of critical path circuits in processing devices such as data processors, very large scale integrated circuits (VLSI), systems on chips (SoCs), central processing units (CPUs), advanced processing units (APUs), graphics processing units (GPUs), memory sub-systems, and system controllers. For example, Automatic Test Pattern Generation (ATPG) may be used to determine if a processing device is operating according to specification. More advanced “at speed” ATPG technologies launch test patterns and capture the resulting data in a manner that tests a functional circuit at substantially the same speed that the functional circuit is intended to operate during normal operation.
During a typical scan test, shift registers are used to shift state information into registers (e.g., a scan chain). The values stored in the registers define the state of corresponding circuit blocks of the processing device under test. The state information may be referred to as a test vector, a test pattern, a scan vector, or a scan pattern. For each test vector, a first capture clock pulse is applied, which initiates propagation of signals through the circuit blocks of the processing device. A second capture clock pulse is applied after a predetermined time interval to capture the results of the logic gate transitions that occur following the first capture clock pulse. The predetermined time interval may be referred to as a cycle time and typically has a value that corresponds to the shortest period or highest frequency of operation of the processing device, i.e., the test is performed “at speed.” The captured results may then be used to determine whether the processing device is functioning correctly or whether one or more scan faults indicate deficiencies in the design or fabrication of the processing device.
A scan set includes a collection of test vectors {V} that are used to verify the fault universe of the processing device. The fault universe may be defined as a collection of all the inputs and outputs of the processing device that are slow-to-rise (e.g., require more than a cycle time to change from a low state to a high state) or are slow to fall (e.g., require more than a cycle time to change from a high state to a low state) when tested at various operating frequencies and voltage pairs. The number of test vectors depends on the total number of testable nodes in the processing device and can range from tens of thousands to hundreds of thousands of vectors per scan set. Testing schemes typically attempt to minimize the total number of test vectors in the scan set to minimize total test time and cost.